Most electrical devices today, which may be ICs or embedded cores within ICs, use scan test architectures to test combinational logic within the devices. Scan test architectures within a device comprise scan paths having externally accessible scan inputs, externally accessible control inputs and externally accessible scan outputs. Alternately, scan test architectures within a device may comprise scan paths having externally accessible scan inputs, externally accessible control inputs and scan outputs that are internally coupled to a compare circuit within the device for comparing the scan outputs with externally accessible expected data inputs. Further, scan test architectures within a device may comprise scan paths having externally accessible scan inputs, externally accessible control inputs and scan outputs internally coupled to a compressor circuit within the device for compressing unmasked scan outputs into a signature. The masking or unmasking of a scan output to the compressor circuit is provided by externally accessible mask data inputs to the circuit.
The expected data inputs to the compare circuit and the mask data inputs to the compressor circuit are provided by additional signal inputs to the device. Requiring a device to have additional inputs for the expected and mask data increases the number of interconnects between the device and a tester. This increase in interconnect increases the cost of the tester, which is reflected in the cost of the device being tested. The present disclosure advantageously provides a way to eliminate the need for a device to have additional inputs for expected and mask data from a tester by allowing the expected and mask data signals to be input to the device from the tester using the scan data inputs of the device. Additional features of the present disclosure, beyond the elimination of expected and mask data inputs, will be described in detail below.